Analysis of Etched drain based Cyl GAA TFET based SRAM cell Design
Darshan Sarode1(darshan.sarode123@gmail.com),
Ribu Mathew1(ribumathew88@gmail.com),
Ankur Beohar1(ankurbeohar16@gmail.com),
Abhishek Kumar Upadhyay2(meetabhishek14@gmail.com)
1School of Electrical and Electronics Engineering, VIT Bhopal, India
2XFAB GmbH, Dresden Germany
Abstract — This paper aims to propose a novel method for designing an SRAM cell using an Etched Drain based Cyl. GAA TFET with a hetero-substrate material and an elevated density strip. The aim is to reduce power dissipation and improve stability, as demonstrated through analysis utilizing SNM as well as N-Curve methods. With respect to the 16nm MOSFET based SRAM cell, the proposed device-based SRAM cell shows significant improvements with a 68.305% reduction in leakage power, a 15.58% increase in SVNM, an 8.623% increase in SINM, an 8.152% increase in WTV, a 12.86% increase in WTI, a 27.62% increase in SPNM, and a 19.95% increase in WTP. The design is implemented and analyzed using Cadence Virtuoso software, and a novel approach of look up tables and Verilog A is utilized for the device to circuit application. These results indicate promising advancements in the design of SRAM cells, which could have significant implications for the development of advanced computer systems.
Keywords— Tunnel Field Effect Transistor (TFET), Static Random Access Memory (SRAM), Static Noise Margin (SNM), Static Voltage Noise Margin(SVNM), Static Current Voltage Margin(SIVM), Write Trip Voltage(WTV), Wire Trip Current(WTI)