Introduction
The packing density of the integrated circuits has increased due to the
growth witnessed by the semiconductor industry, resulting in smaller
components and transistors. One of the crucial components in modern day
electronics is the Static Random-Access Memory cell, but the higher
integration density required for compact memory cell design comes at a
cost of increased leakage current. Standby leakage is a major
contributor to total leakage in low-tech systems, and it significantly
impacts battery life in portable devices. To reduce leakage, the circuit
operates at a lower supply voltage, However, this impedes the circuit’s
speed. Lowering the threshold voltage of transistors reduces delay but
increases leakage, particularly sub-threshold leakage. Design
improvement is important to achieve a memory cell with reduced standby
leakage and improved stability in the face of smaller size and lower
voltages.
To address this constraint, SRAM cell design has been implemented using
Etched Drain based GAA TFET technology, resulting in low power
dissipation and better stability. This design detects Ioff of 1.51 x
10-19 A/um at VGS = 1.5V, Subthreshold
Swing (SS) of 35mV/decade, and Ion/Ioffgreater than 1014 for a threshold voltage of 0.5V.
Stability analysis is conducted using the N-curve method in the Cadence
Virtuoso Environment, using a Verilog A models rooted upon utilization
of lookup tables. In summary, the semiconductor industry’s growth has
resulted in smaller components and transistors, requiring a more compact
memory cell design. However, this comes at a cost of increased leakage
current. The new SRAM cell design using Etched Drain Based GAA TFET
technology aims to address this constraint by reducing power dissipation
and improving stability, making it a promising solution for the next
generation of electronic devices. The focus of this paper is that we are
using a novel approach of implementing SRAM cell using Etched Drain
based Cyl. GAA TFET. The device to circuit application is based on look
up tables and Verilog A approach.