Fig. 2. Device to circuit application algorithm
To address the lack of accurate analytical models for Etched Drain based
GAA TFET, utilizing a Verilog-A device model designed utilizing lookup
table, we were able to achieve both precision and efficiency in compact
modeling for emerging devices. Verification against conventional BSIM
modeling confirms the validity of this approach and is shown in the
figure above, which outlines the simulation methodology used in this
study. To implement this model, we first optimized various parameters
through device simulation. We then generated lookup tables for
Ids, Cgs, and Cgd in
terms of Vgs and Vds using the obtained
I–V and C–V graphs. By integrating these lookup tables into
Verilog-A-based models, they can be employed in conjunction with SPICE
simulation. Lastly, the Cadence Virtuoso tool was utilized to conduct
simulations and measurements of diverse performance metrics for the SRAM
circuit.