Figure 1: Schematics of SWCNT, MWCNT and a CNTFET
Figure 1 shows the schematics of SW-CNT, MW-CNT and a CNTFET. In this work, 32nm technology node n-type CNTFETs with 1V operating voltage, have been used in the CNTFET based CO circuitry, using HSPICE. Further, Verilog-A Stanford model for CNTFET and BSIMv4.6.1 Berkeley Predictive Technology (BPT) for the conventional MOSFET have been used in the simulation study [20, 21-25]. The various CNT parameters used in the simulations include dielectric constant of 16, CNT-diameter (DCNT) of 1.5 nm, inter-CNT pitch (S)-20 nm, threshold voltage (VTH) of 0.49 and the chiral vectors (19,0).