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A Capacitor-Free CMOS Low-Dropout Regulator with Gate-Couple Flipped Voltage Follower for SOC
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  • Yani Li,
  • Fuxiang Tong,
  • Zuoyi Zhang,
  • Zhuo Lv,
  • Linkun Zhang,
  • Zhangming Zhu
Yani Li
Xidian University School of Microelectronics
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Fuxiang Tong
Xidian University School of Microelectronics

Corresponding Author:[email protected]

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Zuoyi Zhang
Xidian University School of Microelectronics
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Zhuo Lv
Xidian University School of Microelectronics
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Linkun Zhang
Xidian University School of Microelectronics
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Zhangming Zhu
Xidian University School of Microelectronics
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Abstract

This paper proposes a fully integrated low dropout (LDO) regulator with gate-couple flipped voltage follower(GC-FVF). The proposed GC-FVF addresses the limited output swing issue of conventional PMOS FVF in LDOs while maintaining a low output impedance. Besides, this LDO introduces a cascode compensation loop, which, along with the low output impedance of GC-FVF, pushes the output pole far away from the unity-gain bandwidth under both light and heavy load conditions. Consequently, the LDO becomes a stable two-pole system, supporting a high loop gain of up to 100dB and significantly enhancing the load and line regulation. Key specifications include a preset output voltage of 1.8V, a minimum unregulated input voltage of 2V, a maximum output current of 100mA, a ground current of 32μA, and an active chip area of 260μm×180μm. Notably, this LDO achieves high load regulation of 4.8μV/mA and high line regulation of 13.8μV/V without the need for off-chip capacitors.
31 Jan 20241st Revision Received
31 Jan 2024Submission Checks Completed
31 Jan 2024Assigned to Editor
31 Jan 2024Review(s) Completed, Editorial Evaluation Pending
11 Feb 2024Reviewer(s) Assigned